Digital logic circuits may be constructed, for example, using complementary metal oxide semiconductor (CMOS) technology. With reference to FIG. 1, in a typical NAND gate 100, a plurality of field effect transistors (FETS) of the p-type (PFETS) 102 can be connected together in parallel between a voltage source 104 and an output 106, to form a first, parallel portion 108. Gates of the PFETS 102 are connected to input terminals, and if any input is active (i.e., in a “LOW” state for a PFET), the supply voltage (VDD) at 104 will appear on the output 106. Prior art NAND gates also include a plurality of n-type FETS (NFETS) 110 interconnected in series or “stacked” fashion to form a second, stacked portion 112. Only if all inputs are active (i.e., “HIGH” for NFETS 110) will output 106 be grounded through stacked portion 112 to ground terminal 114.
Referring now to FIG. 2, in a prior art NOR gate 200, a number of PFETS 202 may be interconnected in series or stacked fashion to form a stacked portion 204 between a voltage supply terminal 206 and an output terminal 208. Furthermore, a plurality of NFETS 210 may be connected in parallel to form a parallel portion 212 between output terminal 208 and ground terminal 214.
It would be desirable to reduce the amount of area occupied by each logic gate. Furthermore, in conventional circuits, the size (i.e., area) for stacked devices must generally be increased to reduced the ON resistance of the gate; this leads to a practical limit on the number of inputs that can be realized in conventional NAND and NOR gates.